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Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip., , , , , , , , and . ARITH, page 37-44. IEEE, (2018)A database accelerator for energy-efficient query processing and optimization., , , , , , , , , and 7 other author(s). NORCAS, page 1-5. IEEE, (2016)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)True random number generation from bang-bang ADPLL jitter., , , and . NORCAS, page 1-5. IEEE, (2016)A deep-submicron CMOS flow for general-purpose timing-detection insertion., , , , and . MIXDES, page 248-253. IEEE, (2015)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)Hardware Implementation of an OPC UA Server for Industrial Field Devices., , , , , , , , , and 6 other author(s). CoRR, (2021)An MPSoC for energy-efficient database query processing., , , , , , , , , and 15 other author(s). DAC, page 112:1-112:6. ACM, (2016)