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The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits., , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 10 (1): 243-254 (2016)A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates., , , , , , , , , and 2 other author(s). ISSCC, page 216-218. IEEE, (2012)Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip., , , , , , , , and . ARITH, page 37-44. IEEE, (2018)A database accelerator for energy-efficient query processing and optimization., , , , , , , , , and 7 other author(s). NORCAS, page 1-5. IEEE, (2016)Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput., , , , , , and . ICECS, page 950-953. IEEE, (2010)Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS., , , , , , , and . CoRR, (2014)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Pattern representation and recognition with accelerated analog neuromorphic systems., , , , , , , , , and 26 other author(s). ISCAS, page 1-4. IEEE, (2017)