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Disambiguation of "Schiefer, Stefan"

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Dynamic Power Management for Neuromorphic Many-Core Systems.

, , , , , , , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)

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Stefan Kunert University of Stuttgart

Stefan Schippling University of Stuttgart

Stefan Hecht University of Stuttgart

Stefan Keuler University of Stuttgart

Dr. -Ing. Stefan Carosella University of Stuttgart

 

Other publications of authors with the same name

Pattern representation and recognition with accelerated analog neuromorphic systems., , , , , , , , , and 25 other author(s). CoRR, (2017)Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system., , , , , , , , , and 19 other author(s). IJCNN, page 2227-2234. IEEE, (2017)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput., , , , , , and . ISCAS, page 1988. IEEE, (2011)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Pattern representation and recognition with accelerated analog neuromorphic systems., , , , , , , , , and 26 other author(s). ISCAS, page 1-4. IEEE, (2017)Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology., , , , and . ECCTD, page 1. IEEE, (2013)Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System., , , , , , , , , and 15 other author(s). CoRR, (2017)