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Implementation and characterization of mixed-signal neuromorphic ASICs.. University of Heidelberg, Germany, (2016)Generative models on accelerated neuromorphic hardware., , , , , , , , , and 14 other author(s). CoRR, (2018)Demonstrating Advantages of Neuromorphic Computation: A Pilot Study., , , , , , , , , and 7 other author(s). CoRR, (2018)Pattern representation and recognition with accelerated analog neuromorphic systems., , , , , , , , , and 25 other author(s). CoRR, (2017)Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system., , , , , , , , , and 19 other author(s). IJCNN, page 2227-2234. IEEE, (2017)Towards biologically realistic multi-compartment neuron model emulation in analog VLSI., , , and . ESANN, (2012)Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System., , , , , and . IEEE Trans. Biomed. Circuits and Systems, 11 (1): 128-142 (2017)An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture., , , , , , , and . IEEE Trans. on Circuits and Systems, 65-I (12): 4299-4312 (2018)Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System., , , , , , , , , and 15 other author(s). CoRR, (2017)An analog dynamic memory array for neuromorphic hardware., , , and . ECCTD, page 1-4. IEEE, (2013)