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An image processing library for C-based high-level synthesis., , , and . FPL, page 1-4. IEEE, (2014)Netlist-level IP protection by watermarking for LUT-based FPGAs., , and . FPT, page 209-216. IEEE, (2008)Code generation from a domain-specific language for C-based HLS of hardware accelerators., , , , and . CODES+ISSS, page 17:1-17:10. ACM, (2014)A deeply pipelined and parallel architecture for denoising medical images., , , and . FPT, page 485-490. IEEE, (2010)System integration of tightly-coupled processor arrays using reconfigurable buffer structures., , , , and . Conf. Computing Frontiers, page 2:1-2:4. ACM, (2013)Big Data and HPC Acceleration with Vivado HLS., , , , , , and . FPGAs for Software Programmers, Springer, (2016)HIPAcc., , , and . FPGAs for Software Programmers, Springer, (2016)Modeling and synthesis of communication subsystems for loop accelerator pipelines., , , and . ASAP, page 125-132. IEEE Computer Society, (2010)Real-timerange image preprocessing on FPGAs., , , and . ReConFig, page 1-8. IEEE, (2013)High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model., , , and . PARCO, volume 25 of Advances in Parallel Computing, page 497-506. IOS Press, (2013)