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High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.

M. Schmid, F. Hannig, A. Tanase, and J. Teich. PARCO, volume 25 of Advances in Parallel Computing, page 497-506. IOS Press, (2013)

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A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.V. Lari, A. Tanase, J. Teich, M. Witterauf, F. Khosravi, F. Hannig, and B. Meyer. AHS, page 1-8. IEEE, (2015)Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.A. Tanase, V. Lari, F. Hannig, and J. Teich. PARCO, volume 25 of Advances in Parallel Computing, page 53-62. IOS Press, (2013)On-demand fault-tolerant loop processing on massively parallel processor arrays.A. Tanase, M. Witterauf, J. Teich, F. Hannig, and V. Lari. ASAP, page 194-201. IEEE Computer Society, (2015)TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays.É. Sousa, A. Chakraborty, A. Tanase, F. Hannig, and J. Teich. ReConFig, page 1-3. IEEE, (2017)Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.É. Sousa, M. Witterauf, M. Brand, A. Tanase, F. Hannig, and J. Teich. ASAP, page 1-9. IEEE Computer Society, (2018)Symbolic inner loop parallelisation for massively parallel processor arrays.A. Tanase, M. Witterauf, J. Teich, and F. Hannig. MEMOCODE, page 219-228. IEEE, (2014)Domain-specific augmentations for High-Level Synthesis.M. Schmid, A. Tanase, F. Hannig, J. Teich, V. Bhadouria, and D. Ghoshal. ASAP, page 173-177. IEEE Computer Society, (2014)Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.M. Witterauf, A. Tanase, F. Hannig, and J. Teich. ASAP, page 58-66. IEEE Computer Society, (2016)A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays.É. Sousa, A. Tanase, F. Hannig, and J. Teich. ReConFig, page 1-8. IEEE, (2017)High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.M. Schmid, F. Hannig, A. Tanase, and J. Teich. PARCO, volume 25 of Advances in Parallel Computing, page 497-506. IOS Press, (2013)

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High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.

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Disambiguation of "Tanase, Alexandru"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.

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High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.