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Disambiguation of "Dutta, Hritam"

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Modeling and synthesis of communication subsystems for loop accelerator pipelines.

, , , and . ASAP, page 125-132. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology., , and . IPDPS, IEEE Computer Society, (2004)Massively Parallel Processor Architectures: A Co-design Approach., , , , , , , , and . ReCoSoC, page 61-68. Univ. Montpellier II, (2007)A holistic approach for tightly coupled reconfigurable parallel processors., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 33 (1): 53-62 (2009)Acceleration of Multiresolution Imaging Algorithms: A Comparative Study., , , , and . ASAP, page 211-214. IEEE Computer Society, (2009)A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., , , , and . ASAP, page 331-340. IEEE Computer Society, (2006)A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation., , , , , and . ERSA, page 14-24. CSREA Press, (2007)Regular mapping for coarse-grained reconfigurable architectures., , and . ICASSP (5), page 57-60. IEEE, (2004)Synthesis and exploration of loop accelerators for systems-on-a-chip.. University of Erlangen-Nuremberg, (2011)Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis., , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 233-245. Springer, (2009)Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning., , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 16-27. Springer, (2009)