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Symbolic system-level design methodology for multi-mode reconfigurable systems., , , and . Design Autom. for Emb. Sys., 17 (2): 343-375 (2013)Power Signature Watermarking of IP Cores for FPGAs., and . Signal Processing Systems, 51 (1): 123-136 (2008)Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems.. CoRR, (2018)Partial Reconfiguration on FPGAs in Practice - Tools and Applications., , , , , , , , and . ARCS Workshops, volume P-200 of LNI, page 297-319. GI, (2012)Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs., and . IJAACS, 2 (3): 256-275 (2009)Netlist-level IP protection by watermarking for LUT-based FPGAs., , and . FPT, page 209-216. IEEE, (2008)Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs.. University of Erlangen-Nuremberg, (2010)FPGA-Based Dynamically Reconfigurable SQL Query Processing., , , , , , , , and . TRETS, 9 (4): 25:1-25:24 (2016)A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks., and . ARCS, volume 10793 of Lecture Notes in Computer Science, page 311-323. Springer, (2018)Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)., , and . CoRR, (2015)