%0 Journal Article %1 journals/ijaacs/ZienerT09 %A Ziener, Daniel %A Teich, Jürgen %D 2009 %J IJAACS %K dblp %N 3 %P 256-275 %T Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. %U http://dblp.uni-trier.de/db/journals/ijaacs/ijaacs2.html#ZienerT09 %V 2

@article{journals/ijaacs/ZienerT09, added-at = {2012-05-29T00:00:00.000+0200}, author = {Ziener, Daniel and Teich, Jürgen}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/245b47526a9c0f62728639d1e303cdba8/dblp}, ee = {http://dx.doi.org/10.1504/IJAACS.2009.026785}, interhash = {98689bb7e3c4eae9e1a0705d2e8d8e17}, intrahash = {45b47526a9c0f62728639d1e303cdba8}, journal = {IJAACS}, keywords = {dblp}, number = 3, pages = {256-275}, timestamp = {2016-02-02T07:51:36.000+0100}, title = {Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.}, url = {http://dblp.uni-trier.de/db/journals/ijaacs/ijaacs2.html#ZienerT09}, volume = 2, year = 2009 }