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Disambiguation of "Ziener, Daniel"

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Netlist-level IP protection by watermarking for LUT-based FPGAs.

, , and . FPT, page 209-216. IEEE, (2008)

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Daniel Holder University of Stuttgart

Laser micromachining of bionic transport structures on cemented tungsten carbide for passive directional transport of lubricants, , , , and . 123, page 452–457. Elsevier BV, (2024)

Dr. -Ing. Daniel Markthaler University of Stuttgart

Replication Data for: Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis, and . Dataset, (2024)Related to: Schneider, Andreas; Lystbæk, Thomas B.; Markthaler, Daniel; Hansen, Niels; Hauer, Bernhard (2024): Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis. In: Nature Communications, 15, 4925. doi: 10.1038/s41467-024-48993-9.

Univ. -Prof. Dr. Daniel Weiskopf University of Stuttgart

Supplemental Materials for: Visual Analysis of Fitness Landscapes in Architectural Design Optimization, , , , , , , and . Software, (2024)Related to: Manuscript accepted for publication in the Visual Computer journal.

Daniel Klötzl University of Stuttgart

NMF-Based Analysis of Mobile Eye-Tracking Data, , , , , , and . Proceedings of the 2024 Symposium on Eye Tracking Research and Applications, page 1–9. New York, NY, USA, Association for Computing Machinery, (Jun 4, 2024)
NMF-Based Analysis of Mobile Eye-Tracking Data, , , , , , and . Proceedings of the 2024 Symposium on Eye Tracking Research and Applications, page 1–9. New York, NY, USA, Association for Computing Machinery, (Jun 4, 2024)Constrained Dynamic Mode Decomposition, , , and . IEEE Transactions on Visualization and Computer Graphics, (2022)

Daniel Marino

 

Other publications of authors with the same name

Symbolic system-level design methodology for multi-mode reconfigurable systems., , , and . Design Autom. for Emb. Sys., 17 (2): 343-375 (2013)Power Signature Watermarking of IP Cores for FPGAs., and . Signal Processing Systems, 51 (1): 123-136 (2008)Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems.. CoRR, (2018)Partial Reconfiguration on FPGAs in Practice - Tools and Applications., , , , , , , , and . ARCS Workshops, volume P-200 of LNI, page 297-319. GI, (2012)FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN)., , , and . ReConFig, page 1-6. IEEE, (2012)On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library., , and . FCCM, page 45-52. IEEE Computer Society, (2012)Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration., , and . FCCM, page 25-28. IEEE Computer Society, (2013)A rapid prototyping system for error-resilient multi-processor systems-on-chip., , , , , , , and . DATE, page 375-380. IEEE, (2010)Stress-Aware Module Placement on Reconfigurable Devices., , , and . FPL, page 277-281. IEEE Computer Society, (2011)A LUT-Based Approximate Adder., , , , and . FCCM, page 27. IEEE Computer Society, (2016)