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Disambiguation of "Lim, Sung Kyu"

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Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.

, and . ASP-DAC, page 175-180. IEEE, (2010)

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Jaekeun Lim University of Stuttgart

 

Other publications of authors with the same name

Backend Dielectric Reliability Full Chip Simulator., , , , and . IEEE Trans. VLSI Syst., 22 (8): 1750-1762 (2014)Distributed TSV Topology for 3-D Power-Supply Networks., and . IEEE Trans. VLSI Syst., 20 (11): 2066-2079 (2012)Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing., , and . IEEE Trans. on Circuits and Systems, 56-II (7): 565-569 (2009)Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs., and . J. Inform. and Commun. Convergence Engineering, (2015)How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study., , and . ISCAS, page 1266-1269. IEEE, (2015)Block-level 3D IC design with through-silicon-via planning., , and . ASP-DAC, page 335-340. IEEE, (2012)Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects., and . ISQED, page 228-335. IEEE, (2012)Physical Planning with Retiming., and . ICCAD, page 2-7. IEEE Computer Society, (2000)Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs., , and . ICCAD, page 379-386. IEEE, (2013)