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A Two-Dimensional, Distributed Logic Architecture., and . IEEE Trans. Computers, 40 (10): 1094-1101 (1991)The Arithmetic Cube., and . IEEE Trans. Computers, 36 (11): 1342-1348 (1987)Polynomial Time Testability of Circuits Generated by Input Decomposition., , and . IEEE Trans. Computers, 43 (2): 201-210 (1994)Area Time Trade-Offs in Micro-Grain VLSI Array Architectures., , and . IEEE Trans. Computers, 43 (10): 1121-1128 (1994)Design Space Exploration for 3-D Cache., , , , and . IEEE Trans. VLSI Syst., 16 (4): 444-455 (2008)Optimising power efficiency in trace cache fetch unit., , , and . IET Computers & Digital Techniques, 1 (4): 334-348 (2007)Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip., , , and . Advances in Computers, (2005)Instruction Scheduling for Low Power., , , , and . VLSI Signal Processing, 37 (1): 129-149 (2004)Reducing non-deterministic loads in low-power caches via early cache set resolution., , and . Microprocessors and Microsystems, 31 (5): 293-301 (2007)Motion Analysis on the Micro Grained Array Processor., , and . Real-Time Imaging, 3 (2): 101-110 (1997)