Author of the publication

Optimising power efficiency in trace cache fetch unit.

, , , and . IET Computers & Digital Techniques, 1 (4): 334-348 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip., , , and . Advances in Computers, (2005)CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors., , , , and . DSD, page 41-49. IEEE Computer Society, (2003)Distributed Fault Diagnosis in the Butterfly Parallel Processor., , , and . ICPP (1), page 172-175. Pennsylvania State University Press, (1989)Numerical limitations on the design of digit online networks., and . IEEE Symposium on Computer Arithmetic, page 156-161. IEEE Computer Society, (1983)Design Space Exploration for 3-D Cache., , , , and . IEEE Trans. VLSI Syst., 16 (4): 444-455 (2008)Area Time Trade-Offs in Micro-Grain VLSI Array Architectures., , and . IEEE Trans. Computers, 43 (10): 1121-1128 (1994)A Two-Dimensional, Distributed Logic Architecture., and . IEEE Trans. Computers, 40 (10): 1094-1101 (1991)Optimising power efficiency in trace cache fetch unit., , , and . IET Computers & Digital Techniques, 1 (4): 334-348 (2007)The Arithmetic Cube., and . IEEE Trans. Computers, 36 (11): 1342-1348 (1987)Polynomial Time Testability of Circuits Generated by Input Decomposition., , and . IEEE Trans. Computers, 43 (2): 201-210 (1994)