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Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design., , , and . DATE, page 983-988. European Design and Automation Association, Leuven, Belgium, (2006)Double-gate SOI devices for low-power and high-performance applications., , , , , and . ICCAD, page 217-224. IEEE Computer Society, (2005)Yield estimation of SRAM circuits using "Virtual SRAM Fab"., , , , , , , , , and 2 other author(s). ICCAD, page 631-636. ACM, (2009)Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability., , , , , and . Microelectronics Reliability, 49 (6): 642-649 (2009)Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (11): 2059-2068 (2007)Double-Gate SOI Devices for Low-Power and High-Performance Applications., , , , , and . VLSI Design, page 445-452. IEEE Computer Society, (2006)A high density, carbon nanotube capacitor for decoupling applications., , , and . DAC, page 935-938. ACM, (2006)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module., , , , , , , , , and 15 other author(s). J. Solid-State Circuits, 49 (1): 9-18 (2014)Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era., , and . CICC, page 835-838. IEEE, (2005)Covariance computation in MHE: A nonlinear regression approach., , and . ICCA, page 663-668. IEEE, (2016)