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Disambiguation of "Mukhopadhyay, Saibal"

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Double-gate SOI devices for low-power and high-performance applications.

, , , , , and . ICCAD, page 217-224. IEEE Computer Society, (2005)

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Other publications of authors with the same name

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics., , , , , and . J. Solid-State Circuits, 44 (3): 965-976 (2009)An energy-efficient wireless video sensor node with a region-of-interest based multi-parameter rate controller for moving object surveillance., , and . AVSS, page 138-144. IEEE Computer Society, (2016)Postsilicon Adaptation for Low-Power SRAM under Process Variation., , , , and . IEEE Design & Test of Computers, 27 (6): 26-35 (2010)Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies., , , and . ISCAS, page 384-387. IEEE, (2008)Process Variation Tolerant Online Current Monitor for Robust Systems., , , and . IOLTS, page 171-176. IEEE Computer Society, (2005)Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies., , , , and . DATE, page 926-931. IEEE Computer Society, (2005)A Novel Low-Power Scan Design Technique Using Supply Gating., , , , and . ICCD, page 60-65. IEEE Computer Society, (2004)Guest Editorial Computing in Emerging Technologies (First Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 377-379 (2014)Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications., , , and . ASP-DAC, page 823-828. IEEE, (2009)Gate leakage reduction for scaled devices using transistor stacking., , , , , and . IEEE Trans. VLSI Syst., 11 (4): 716-730 (2003)