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Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.

S. Mukhopadhyay, R. Rao, J. Kim, and C. Chuang. ISCAS, page 384-387. IEEE, (2008)

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Rahul Barthwal University of Stuttgart

M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

Other publications of authors with the same name

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.N. Dhanwada, D. Hathaway, V. Zyuban, P. Peng, K. Moody, W. Dungan, A. Joseph, R. Rao, and C. Gonzalez. ICCAD, page 458-465. IEEE, (2013)IBM POWER8 circuit design and energy optimization.V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam and 13 other author(s). IBM Journal of Research and Development, (2015)IBM POWER9 circuit design and energy optimization for 14-nm technology.E. Fluhr, R. Rao, H. Smith, A. Buyuktosunoglu, and R. Monfort. IBM Journal of Research and Development, 62 (4/5): 4 (2018)A High Performance Gated Voltage Level Translator with Integrated Multiplexer.D. S., and R. Rao. VLSI Design, page 358-361. IEEE Computer Society, (2018)A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.R. Rao, F. Liu, J. Burns, and R. Brown. ICCAD, page 689-692. IEEE Computer Society / ACM, (2003)Efficient techniques for gate leakage estimation.R. Rao, J. Burns, A. Devgan, and R. Brown. ISLPED, page 100-103. ACM, (2003)A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry.R. Rao, K. Jenkins, and J. Kim. J. Solid-State Circuits, 44 (9): 2616-2623 (2009)Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.H. Deogun, D. Sylvester, R. Rao, and K. Nowka. SoCC, page 147-150. IEEE, (2005)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.A. Ghosh, R. Rao, C. Chuang, and R. Brown. ISQED, page 815-820. IEEE Computer Society, (2008)Impact of Device Aging on Early Mode Failures in Pulsed Latches.A. Shukla, R. Rao, and J. Warnock. VLSI Design, page 256-260. IEEE Computer Society, (2018)

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Disambiguation of "Rao, Rahul M."

Please choose a person to relate this publication to

Rahul Barthwal University of Stuttgart

M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Rao, Rahul M."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.

Please choose a person to relate this publication to

Rahul Barthwal University of Stuttgart

M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

Other publications of authors with the same name

Disambiguation