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Stream Computations Organized for Reconfigurable Execution (SCORE)., , , , , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 605-614. Springer, (2000)Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine., , , , , , and . FPGA, page 196-205. ACM, (2002)Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA., , , , and . FCCM, page 135. IEEE Computer Society, (2017)Stochastic spatial routing for reconfigurable networks., , and . Microprocessors and Microsystems, 30 (6): 301-318 (2006)Hardware-Assisted Fast Routing., , and . FCCM, page 205-. IEEE Computer Society, (2002)Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA., , , , and . HPEC, page 1-7. IEEE, (2017)Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?, , , , , , , , , and 1 other author(s). FPGA, page 5-14. ACM, (2017)Stochastic, spatial routing for hypergraphs, trees, and meshes., , and . FPGA, page 78-87. ACM, (2003)HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array., , , , , , , , , and . FPGA, page 125-134. ACM, (1999)Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper., and . ISLPED, page 152-153. ACM, (2016)