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Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

E. Nurvitadhi, G. Venkatesh, J. Sim, D. Marr, R. Huang, J. Hock, Y. Liew, K. Srivatsan, D. Moss, S. Subhaschandra, and G. Boudoukh. FPGA, page 5-14. ACM, (2017)

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Ganesh Deepak Rupakula University of Stuttgart

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Hardware accelerator for analytics of sparse data.E. Nurvitadhi, A. Mishra, Y. Wang, G. Venkatesh, and D. Marr. DATE, page 1616-1621. IEEE, (2016)Mixed Precision Training.P. Micikevicius, S. Narang, J. Alben, G. Diamos, E. Elsen, D. García, B. Ginsburg, M. Houston, O. Kuchaiev, G. Venkatesh and 1 other author(s). CoRR, (2017)Efficient complex operators for irregular codes.J. Sampson, G. Venkatesh, N. Goulding-Hotta, S. Garcia, S. Swanson, and M. Taylor. HPCA, page 491-502. IEEE Computer Society, (2011)Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors.B. Li, G. Venkatesh, B. Calder, and R. Gupta. HiPEAC, volume 3793 of Lecture Notes in Computer Science, page 251-265. Springer, (2005)Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.M. Arora, J. Sampson, N. Goulding-Hotta, J. Babb, G. Venkatesh, M. Taylor, and S. Swanson. FCCM, page 210-213. IEEE Computer Society, (2011)Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?E. Nurvitadhi, G. Venkatesh, J. Sim, D. Marr, R. Huang, J. Hock, Y. Liew, K. Srivatsan, D. Moss, S. Subhaschandra and 1 other author(s). FPGA, page 5-14. ACM, (2017)QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.G. Venkatesh, J. Sampson, N. Goulding-Hotta, S. Venkata, M. Taylor, and S. Swanson. MICRO, page 163-174. ACM, (2011)Runnemede: An architecture for Ubiquitous High-Performance Computing.N. Carter, A. Agrawal, S. Borkar, R. Cledat, H. David, D. Dunning, J. Fryman, I. Ganev, R. Golliver, R. Knauerhase and 9 other author(s). HPCA, page 198-209. IEEE Computer Society, (2013)Mixed Precision Training.P. Micikevicius, S. Narang, J. Alben, G. Diamos, E. Elsen, D. García, B. Ginsburg, M. Houston, O. Kuchaiev, G. Venkatesh and 1 other author(s). ICLR (Poster), OpenReview.net, (2018)An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.J. Sampson, M. Arora, N. Goulding-Hotta, G. Venkatesh, J. Babb, V. Bhatt, S. Swanson, and M. Taylor. FPL, page 24-29. IEEE Computer Society, (2011)

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Disambiguation of "Venkatesh, Ganesh"

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Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

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Ganesh Deepak Rupakula University of Stuttgart

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PUMA

Disambiguation of "Venkatesh, Ganesh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

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Ganesh Deepak Rupakula University of Stuttgart

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Disambiguation

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Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?