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Stream Computations Organized for Reconfigurable Execution (SCORE).

E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon. FPL, volume 1896 of Lecture Notes in Computer Science, page 605-614. Springer, (2000)

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Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Dr. -Ing. Min Huang University of Stuttgart

Shih-Min Huang University of Stuttgart

Other publications of authors with the same name

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.Y. Markovsky, E. Caspi, R. Huang, J. Yeh, M. Chu, J. Wawrzynek, and A. DeHon. FPGA, page 196-205. ACM, (2002)Stream Computations Organized for Reconfigurable Execution (SCORE).E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon. FPL, volume 1896 of Lecture Notes in Computer Science, page 605-614. Springer, (2000)Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA.P. Colangelo, R. Huang, E. Lübbers, M. Margala, and K. Nealis. FCCM, page 135. IEEE Computer Society, (2017)Stochastic spatial routing for reconfigurable networks.A. DeHon, R. Huang, and J. Wawrzynek. Microprocessors and Microsystems, 30 (6): 301-318 (2006)Hardware-Assisted Fast Routing.A. DeHon, R. Huang, and J. Wawrzynek. FCCM, page 205-. IEEE Computer Society, (2002)Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA.P. Colangelo, E. Lübbers, R. Huang, M. Margala, and K. Nealis. HPEC, page 1-7. IEEE, (2017)Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?E. Nurvitadhi, G. Venkatesh, J. Sim, D. Marr, R. Huang, J. Hock, Y. Liew, K. Srivatsan, D. Moss, S. Subhaschandra and 1 other author(s). FPGA, page 5-14. ACM, (2017)Stochastic, spatial routing for hypergraphs, trees, and meshes.R. Huang, J. Wawrzynek, and A. DeHon. FPGA, page 78-87. ACM, (2003)Stream computations organized for reconfigurable execution.A. DeHon, Y. Markovsky, E. Caspi, M. Chu, R. Huang, S. Perissakis, L. Pozzi, J. Yeh, and J. Wawrzynek. Microprocessors and Microsystems, 30 (6): 334-354 (2006)Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper.H. Schmit, and R. Huang. ISLPED, page 152-153. ACM, (2016)