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Memory Reliability Improvement Based on Maximized Error-Correcting Codes.

, , and . J. Electronic Testing, 29 (4): 601-608 (2013)

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Programmable extended SEC-DED codes for memory errors., , , and . VTS, page 140-145. IEEE Computer Society, (2011)Memory Reliability Improvement Based on Maximized Error-Correcting Codes., , and . J. Electronic Testing, 29 (4): 601-608 (2013)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection., , , , and . DATE, page 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Memory reliability improvements based on maximized error-correcting codes., , and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Programmable restricted SEC codes to mask permanent faults in semiconductor memories., , and . IOLTS, page 147-153. IEEE Computer Society, (2010)Power-Driven Routing-Constrained Scan Chain Design., , , , and . J. Electronic Testing, 20 (6): 647-660 (2004)An efficient scan tree design for test time reduction., , , and . European Test Symposium, page 174-179. IEEE Computer Society, (2004)Transaction-based modeling for large scale simulations of heterogeneous systems., , and . SimuTools, page 33. ICST/ACM, (2009)A Gated Clock Scheme for Low Power Testing of Logic Cores., , , , , and . J. Electronic Testing, 22 (1): 89-99 (2006)A Gated Clock Scheme for Low Power Scan-Based BIST., , , , and . IOLTW, page 87-89. IEEE Computer Society, (2001)