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Disambiguation of "Fujiwara, Hideo"

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An efficient scan tree design for test time reduction.

, , , and . European Test Symposium, page 174-179. IEEE Computer Society, (2004)

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Other publications of authors with the same name

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints., , , , , and . J. Electronic Testing, 28 (4): 511-521 (2012)Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption., , and . J. Electronic Testing, 18 (1): 55-62 (2002)New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency., , and . J. Electronic Testing, 20 (3): 315-323 (2004)A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint., , and . ATS, page 27-34. IEEE Computer Society, (2008)Untestable Fault Identification in Sequential Circuits Using Model-Checking., , , and . ATS, page 21-26. IEEE Computer Society, (2008)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (9): 1105-1113 (2002)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (12): 1446-1458 (2002)System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. VLSI Syst., 14 (3): 305-309 (2006)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)Secure scan design using shift register equivalents against differential behavior attack., , and . ASP-DAC, page 818-823. IEEE, (2011)