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Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

, , , , and . DATE, page 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs., , , , and . Microelectronics Reliability, 53 (9-11): 1189-1193 (2013)Exploring the feasibility of selective hardening for combinational logic., , , and . Microelectronics Reliability, 52 (9-10): 1843-1847 (2012)Cross-layer investigation of continuous-time sigma-delta modulator under aging effects., , , , , and . Microelectronics Reliability, 55 (3-4): 645-653 (2015)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection., , , , and . DATE, page 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction., , , , and . NEWCAS, page 1-4. IEEE, (2015)Efficient implementation for accurate analysis of CED circuits against multiple faults., , , and . MIXDES, page 436-440. IEEE, (2014)Parallel scaling-free and area-time efficient CORDIC algorithm., , and . ICECS, page 149-152. IEEE, (2012)A new fault-tolerant architecture for CLBs in SRAM-based FPGAs., , and . ICECS, page 761-764. IEEE, (2012)Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths., , , , and . IOLTS, page 160-163. IEEE, (2014)Efficient reliability evaluation methodologies for combinational circuits., , , , , and . Microelectronics Reliability, (2016)