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Disambiguation of "Lee, Chung-Len"

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Modeling and testing of interference faults in the nano NAND Flash memory.

, , and . DATE, page 527-531. IEEE, (2012)

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Joachim Lentes University of Stuttgart

Competitive and sustainable manufacturing by means of ultra-efficient factories in urban surroundings, , , , , and . International journal of production research, 55 (2): 480-491 (2017)

Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Phi-Long Chung University of Stuttgart

 

Other publications of authors with the same name

Functional test pattern generation for CMOS operational amplifier., , and . VTS, page 267-273. IEEE Computer Society, (1997)Fault diagnosis for linear analog circuits., , , and . Asian Test Symposium, page 25-30. IEEE Computer Society, (2000)Panel: New Research Problems in the Emerging Test Technology., , , , , , and . Asian Test Symposium, page 189-190. IEEE Computer Society, (1995)Fault diagnosis of odd-even sorting networks., , , and . Asian Test Symposium, page 288-. IEEE Computer Society, (1997)A New Path Delay Test Scheme Based on Path Delay Inertia., , and . Asian Test Symposium, page 140-144. IEEE Computer Society, (2004)TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator., , and . EDAC-ETC-EUROASIC, page 508-512. IEEE Computer Society, (1994)A novel test scheme for NAND flash memory based on built-in oscillator ring., , and . ASICON, page 1-4. IEEE, (2013)New DfT architectures for 3D-SICs with a wireless test port., , , , and . ASICON, page 1-4. IEEE, (2013)A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines., and . IEEE Trans. Computers, 45 (9): 1079-1083 (1996)Simplifying Sequential Circuit Test Generation., and . IEEE Design & Test of Computers, 11 (3): 28-38 (1994)