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Panel: New Research Problems in the Emerging Test Technology.

, , , , , , and . Asian Test Symposium, page 189-190. IEEE Computer Society, (1995)

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Reducing Power Dissipation during At-Speed Test Application., , and . DFT, page 116-. IEEE Computer Society, (2001)A New Software Testing Approach Based on Domain Analysis of Specifications and Programs., , and . ISSRE, page 60-70. IEEE Computer Society, (2003)Memory Efficient ATPG for Path Delay Faults., , , and . Asian Test Symposium, page 326-331. IEEE Computer Society, (1997)Timed Binary Decision Diagrams., , , and . ICCD, page 352-357. IEEE Computer Society, (1997)Reduction of Number of Paths to be Tested in Delay Testing., , and . J. Electronic Testing, 16 (5): 477-485 (2000)Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers., , and . FTCS, page 238-247. IEEE Computer Society, (1995)The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications., , , and . Science in China Series F: Information Sciences, 45 (6): 401-415 (2002)A kind of Multistage Interconnection Networks with multiple paths., and . J. Comput. Sci. Technol., 11 (4): 395-404 (1996)IDDT: Fundamentals and Test Generation., , , and . J. Comput. Sci. Technol., 18 (3): 299-307 (2003)Short-time scaling of variable ordering of OBDDs., , , and . J. Comput. Sci. Technol., 12 (4): 366-371 (1997)