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Disambiguation of "Reviriego, Pedro"

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Optimizing the Implementation of SEC-DAEC Codes in FPGAs.

, , and . IEEE Trans. VLSI Syst., 24 (12): 3538-3542 (2016)

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Dr. Elisete Pedrollo University of Stuttgart

 

Other publications of authors with the same name

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs., , and . Microelectronics Reliability, (2016)Mitigation of permanent faults in adaptive equalizers., , and . Microelectronics Reliability, 51 (3): 703-710 (2011)Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation., , and . IEEE Trans. VLSI Syst., 21 (12): 2334-2338 (2013)A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets., and . Microelectronics Reliability, 49 (7): 707-715 (2009)Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters., , and . IEEE Trans. on Circuits and Systems, 58-II (8): 512-516 (2011)Efficient Soft Error-Tolerant Adaptive Equalizers., , and . IEEE Trans. on Circuits and Systems, 57-I (8): 2032-2040 (2010)Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes., , , and . IEEE Trans. Computers, 64 (5): 1497-1501 (2015)An Initial Evaluation of Energy Efficient Ethernet., , , and . IEEE Communications Letters, 15 (5): 578-580 (2011)Performance evaluation of energy efficient ethernet., , , and . IEEE Communications Letters, 13 (9): 697-699 (2009)Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication., , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-D): 1103-1107 (2013)