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Disambiguation of "Nikoubin, Tooraj"

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A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic.

, , , and . J. Low Power Electronics, 5 (4): 474-483 (2009)

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Other publications of authors with the same name

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits., , , , and . VLSI Design, (2010)A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic., , , and . J. Low Power Electronics, 5 (4): 474-483 (2009)Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology., , and . IEEE Trans. VLSI Syst., 24 (1): 398-402 (2016)Complement Based Logic Design (CBLD) for Area and Power Efficiency of Arithmetic Building Blocks., , and . ICCCNT, page 13:1-13:6. ACM, (2016)Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures., , , and . ICCCNT, page 10:1-10:5. ACM, (2016)Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style., , and . J. Low Power Electronics, 6 (4): 503-512 (2010)Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic., , , and . Microelectronics Journal, 44 (12): 1238-1250 (2013)Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures., , and . IEEE Trans. VLSI Syst., 27 (5): 1138-1147 (2019)Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells., and . IEEE Access, (2019)High Speed, Area and Power Efficient 32-bit Vedic Multipliers., , , and . ICCCNT, page 11:1-11:7. ACM, (2016)