%0 Journal Article %1 journals/tvlsi/BasireddyCN19 %A Basireddy, Hareesh-Reddy %A Challa, Karthikeya %A Nikoubin, Tooraj %D 2019 %J IEEE Trans. VLSI Syst. %K dblp %N 5 %P 1138-1147 %T Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#BasireddyCN19 %V 27

@article{journals/tvlsi/BasireddyCN19, added-at = {2019-05-31T00:00:00.000+0200}, author = {Basireddy, Hareesh-Reddy and Challa, Karthikeya and Nikoubin, Tooraj}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27753ae50a50dede2ba1386bbdb4ec9c8/dblp}, ee = {https://doi.org/10.1109/TVLSI.2018.2889833}, interhash = {71ce727a705a70986ac4b76f4b96f1ee}, intrahash = {7753ae50a50dede2ba1386bbdb4ec9c8}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 5, pages = {1138-1147}, timestamp = {2019-09-27T06:53:33.000+0200}, title = {Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#BasireddyCN19}, volume = 27, year = 2019 }