PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Choudhury, Mihir R."

Author of the publication

copydeleteadd this publication to your clipboard
Bridging high performance and low power in processor design.

, , , and . ISLPED, page 183-188. ACM, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

R. Leister

R. Koerner

R. Watty

Univ. -Prof. Dr. -Ing. Jörg Roth-Stielow University of Stuttgart

LETSCOPE : Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics, , , , , , , , , and 3 other author(s). IEEE EUROCON 2023 : 20th International Conference on Smart Technologies, page 665-670. IEEE, (2023)

Julian Raible University of Stuttgart

Artificial Neural Network Guided Compensation of Nonlinear Payload and Wear Effects for Industrial Robots, , , , , , , , , and . 2023 IEEE 19th International Conference on Automation Science and Engineering (CASE), IEEE, (2023)
 

Other publications of authors with the same name

Low Cost Concurrent Error Masking Using Approximate Logic Circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (8): 1163-1176 (2013)Reliability-driven don't care assignment for logic synthesis., , and . DATE, page 1560-1565. IEEE, (2011)Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs., , , and . ASP-DAC, page 249-254. IEEE, (2015)NeuNetS: An Automated Synthesis Engine for Neural Network Design., , , , , , , , , and 10 other author(s). CoRR, (2019)Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience., , , and . IEEE Trans. Computers, 63 (2): 497-509 (2014)Masking timing errors on speed-paths in logic circuits., and . DATE, page 87-92. IEEE, (2009)Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion., , and . J. Electronic Testing, 25 (2-3): 197-207 (2009)Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (5): 820-831 (2016)Approximate logic circuits for low overhead, non-intrusive concurrent error detection., and . DATE, page 903-908. ACM, (2008)Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques., , and . ICCAD, page 204-209. ACM, (2006)