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Disambiguation of "Yilmaz, Mahmut"

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The scan-DFT features of AMD's next-generation microprocessor core.

, , , , , , , , and . ITC, page 39-48. IEEE Computer Society, (2010)

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Seda Yilmaz University of Stuttgart

Mahmut Yorulmaz University of Stuttgart

Merve Yilmaz University of Stuttgart

Zeynep Hazal Yilmaz University of Stuttgart

 

Other publications of authors with the same name

Flexible scan interface architecture for complex SoCs., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Test-Pattern Grading and Pattern Selection for Small-Delay Defects., , and . VTS, page 233-239. IEEE Computer Society, (2008)Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 760-773 (2010)Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization., , and . Asian Test Symposium, page 290-295. IEEE Computer Society, (2012)The scan-DFT features of AMD's next-generation microprocessor core., , , , , , , , and . ITC, page 39-48. IEEE Computer Society, (2010)Critical Fault-Based Pattern Generation for Screening SDDs., , , , , and . European Test Symposium, page 177-182. IEEE Computer Society, (2011)Advanced test methodology for complex SoCs., , , , , , and . ITC, page 1-10. IEEE, (2016)RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage., , , and . ITC, page 625-634. IEEE Computer Society, (2010)Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects., , , and . IEEE Trans. VLSI Syst., 21 (6): 1129-1142 (2013)Circuit Topology-Based Test Pattern Generation for Small-Delay Defects., , , , and . Asian Test Symposium, page 307-312. IEEE Computer Society, (2010)