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Disambiguation of "Fujiwara, Hideo"

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RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.

, , , and . ITC, page 625-634. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Test pattern selection to optimize delay test quality with a limited size of test set., , , , and . European Test Symposium, page 260. IEEE Computer Society, (2010)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)Secure scan design using shift register equivalents against differential behavior attack., , and . ASP-DAC, page 818-823. IEEE, (2011)Localized random access scan: Towards low area and routing overhead., , , and . ASP-DAC, page 565-570. IEEE, (2008)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , and . DISC, volume 5805 of Lecture Notes in Computer Science, page 172-173. Springer, (2009)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , and . WDAG, volume 1320 of Lecture Notes in Computer Science, page 290-304. Springer, (1997)A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order., , , and . Graph Drawing, volume 1547 of Lecture Notes in Computer Science, page 183-197. Springer, (1998)Non-scan design for testable data paths using thru operation., , , and . ASP-DAC, page 313-318. IEEE, (1997)Power-constrained test scheduling for multi-clock domain SoCs., , and . DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)