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Disambiguation of "Fujiwara, Hideo"

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Non-scan design for testable data paths using thru operation.

, , , and . ASP-DAC, page 313-318. IEEE, (1997)

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Other publications of authors with the same name

A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distrib. Comput., 62 (5): 865-884 (2002)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. VLSI Syst., 15 (7): 790-800 (2007)The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. on Circuits and Systems, 54-II (5): 450-454 (2007)A random-pattern testable design for programmable logic arrays.. Systems and Computers in Japan, 18 (7): 95-102 (1987)An approach to test synthesis from higher level., and . Integration, 26 (1-2): 101-116 (1998)A cost optimal parallel algorithm for weighted distance transforms., , , and . Parallel Computing, 25 (4): 405-416 (1999)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Transactions, 88-D (8): 1940-1947 (2005)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Transactions, 89-D (4): 1490-1497 (2006)Effect of BIST Pretest on IC Defect Level., , and . IEICE Transactions, 89-D (10): 2626-2636 (2006)