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Multi-level qualitative reasoning applied to CMOS digital circuits.

N. Kaul, G. Biswas, und B. Bhuva. AI in Engineering, 7 (3): 125-137 (1992)

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L. Ahlgrimm

Lambert Theisen University of Stuttgart

Annika Liebgott

Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classificationS. Gatidis, A. Liebgott, M. Schwartz, P. Martirosian, F. Schick, K. Nikolaou, B. Yang, und T. Küstner. Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)

Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classificationS. Gatidis, A. Liebgott, M. Schwartz, P. Martirosian, F. Schick, K. Nikolaou, B. Yang, und T. Küstner. Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)An easy-to-use image labeling platform for automatic Magnetic Resonance Image Quality AssessmentT. Küstner, P. Wolf, M. Schwartz, A. Liebgott, F. Schick, S. Gatidis, und B. Yang. Proceedings of the IEEE International Symposium on Biomedical Imaging (ISBI), Melbourne, Australia, (April 2017)Automated image quality assessment in whole-body MRIS. Gatidis, A. Liebgott, H. Schmidt, N. Schwenzer, P. Martirosian, K. Nikolaou, F. Schick, B. Yang, und T. Küstner. Proceedings of the Radiological Society of North America (RSNA), Chicago, USA, (November 2016)

Univ. -Prof. Dr. Remco Ingmar Leine University of Stuttgart

Dr. -Ing. Bernhardt Lüddecke University of Stuttgart

Weitere Publikationen von Autoren mit dem selben Namen

Statistical degradation analysis of digital CMOS IC's.V. Rangavajjhala, B. Bhuva, und S. Kerns. IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (6): 837-844 (1993)Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.D. Limbrick, S. Yue, W. Robinson, und B. Bhuva. DFT, Seite 103-111. IEEE Computer Society, (2011)Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.D. Rennie, D. Li, M. Sachdev, B. Bhuva, S. Jagannathan, S. Wen, und R. Wong. IEEE Trans. on Circuits and Systems, 59-I (8): 1626-1634 (2012)Terrestrial SER characterization for nanoscale technologies: A comparative study.N. Mahatme, B. Bhuva, N. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, B. Narasimham, A. Shih, S. Wen und 5 andere Autor(en). IRPS, Seite 4. IEEE, (2015)Multi-level qualitative reasoning applied to CMOS digital circuits.N. Kaul, G. Biswas, und B. Bhuva. AI in Engineering, 7 (3): 125-137 (1992)An efficient technique to select logic nodes for single event transient pulse-width reduction.N. Mahatme, I. Chatterjee, A. Patki, D. Limbrick, B. Bhuva, R. Schrimpf, und W. Robinson. Microelectronics Reliability, 53 (1): 114-117 (2013)A TCAD evaluation of a single Bulk-BICS with integrative memory cell.A. Simionovski, G. Wirth, R. Schrimpf, und B. Bhuva. Microelectronics Journal, (2018)Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter.Y. Ren, L. Fan, L. Chen, S. Wen, R. Wong, N. van Vonno, A. Witulski, und B. Bhuva. J. Electronic Testing, 28 (6): 877-883 (2012)Multi-cell soft errors at the 16-nm FinFET technology node.N. Tam, B. Bhuva, L. Massengill, D. Ball, M. McCurdy, M. Alles, und I. Chatterjee. IRPS, Seite 4. IEEE, (2015)Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.B. Narasimham, K. Chandrasekharan, J. Wang, und B. Bhuva. IRPS, Seite 1-4. IEEE, (2019)