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Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

B. Narasimham, K. Chandrasekharan, J. Wang, and B. Bhuva. IRPS, page 1-4. IEEE, (2019)

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Rachna Balaji University of Stuttgart

Nidish Narayanaa Balaji University of Stuttgart

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Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.B. Narasimham, K. Chandrasekharan, J. Wang, and B. Bhuva. IRPS, page 1-4. IEEE, (2019)Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.J. Cao, L. Xu, B. Bhuva, S. Wen, R. Wong, B. Narasimham, and L. Massengill. IRPS, page 1-5. IEEE, (2019)Designing soft-error-aware circuits with power and speed optimization.H. Jiang, H. Zhang, B. Narasimham, L. Massengill, and B. Bhuva. IRPS, page 5-1. IEEE, (2018)Terrestrial SER characterization for nanoscale technologies: A comparative study.N. Mahatme, B. Bhuva, N. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, B. Narasimham, A. Shih, S. Wen and 5 other author(s). IRPS, page 4. IEEE, (2015)Evaluation of the system-level SER performance of gigabit ethernet transceiver devices.B. Narasimham, T. Wu, J. Wang, and B. Conway. IRPS, page 4. IEEE, (2018)Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs.B. Narasimham, J. Wang, N. Vedula, S. Gupta, B. Bartz, C. Monzel, I. Chatterjee, B. Bhuva, R. Schrimpf, and R. Reed. IRPS, page 2. IEEE, (2015)Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs.B. Narasimham, S. Gupta, D. Reed, J. Wang, N. Hendrickson, and H. Taufique. IRPS, page 4. IEEE, (2018)Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology.H. Zhang, H. Jiang, M. Eaker, K. Lezon, B. Narasimham, N. Mahatme, L. Massengill, and B. Bhuva. IRPS, page 1. IEEE, (2018)

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Disambiguation of "Narasimham, Balaji"

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Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

Please choose a person to relate this publication to

Rachna Balaji University of Stuttgart

Nidish Narayanaa Balaji University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Narasimham, Balaji"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

Please choose a person to relate this publication to

Rachna Balaji University of Stuttgart

Nidish Narayanaa Balaji University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
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Chicago
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Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.