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Disambiguation of "Janapsatya, Andhi"

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Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.

, , , and . DATE, page 920-925. IEEE, (2010)

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Other publications of authors with the same name

Optimization of instruction memory for embedded systems.. University of New South Wales, Sydney, Australia, (2005)base-search.net (ftunswworks:oai:unsworks.library.unsw.edu.au:1959.4/24210).Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm., , , and . DATE, page 920-925. IEEE, (2010)A novel instruction scratchpad memory optimization method based on concomitance metric., , and . ASP-DAC, page 612-617. IEEE, (2006)DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy., , , and . DATE, page 496-501. IEEE, (2010)Rapid Embedded Hardware/Software System Generation., , , and . VLSI Design, page 111-116. IEEE Computer Society, (2005)HitME: low power Hit MEmory buffer for embedded systems., , and . ASP-DAC, page 335-340. IEEE, (2009)SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy., , , and . DAC, page 356-361. ACM, (2010)Hardware/software managed scratchpad memory for embedded system., , and . ICCAD, page 370-377. IEEE Computer Society / ACM, (2004)Rapid runtime estimation methods for pipelined MPSoCs., , , and . DATE, page 363-368. IEEE, (2010)Instruction trace compression for rapid instruction cache simulation., , , and . DATE, page 803-808. EDA Consortium, San Jose, CA, USA, (2007)