%0 Conference Paper %1 conf/dac/HaquePJP10 %A Haque, Mohammad Shihabul %A Peddersen, Jorgen %A Janapsatya, Andhi %A Parameswaran, Sri %B DAC %D 2010 %E Sapatnekar, Sachin S. %I ACM %K dblp %P 356-361 %T SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. %U http://dblp.uni-trier.de/db/conf/dac/dac2010.html#HaquePJP10 %@ 978-1-4503-0002-5

@inproceedings{conf/dac/HaquePJP10, added-at = {2018-11-06T00:00:00.000+0100}, author = {Haque, Mohammad Shihabul and Peddersen, Jorgen and Janapsatya, Andhi and Parameswaran, Sri}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2255b6c019890bec91b4dd9a44f449955/dblp}, booktitle = {DAC}, crossref = {conf/dac/2010}, editor = {Sapatnekar, Sachin S.}, ee = {https://doi.org/10.1145/1837274.1837364}, interhash = {9c8cbf9c2f7bd5fdbf0eeb598b012f5c}, intrahash = {255b6c019890bec91b4dd9a44f449955}, isbn = {978-1-4503-0002-5}, keywords = {dblp}, pages = {356-361}, publisher = {ACM}, timestamp = {2019-09-27T20:19:14.000+0200}, title = {SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2010.html#HaquePJP10}, year = 2010 }