%0 Conference Paper %1 conf/aspdac/JanapsatyaIP06 %A Janapsatya, Andhi %A Ignjatovic, Aleksandar %A Parameswaran, Sri %B ASP-DAC %D 2006 %E Hirose, Fumiyasu %I IEEE %K dblp %P 612-617 %T A novel instruction scratchpad memory optimization method based on concomitance metric. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#JanapsatyaIP06 %@ 0-7803-9451-8

@inproceedings{conf/aspdac/JanapsatyaIP06, added-at = {2018-11-06T00:00:00.000+0100}, author = {Janapsatya, Andhi and Ignjatovic, Aleksandar and Parameswaran, Sri}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b7a7accbb0409b6f80f2056175dc1a80/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2006}, editor = {Hirose, Fumiyasu}, ee = {https://doi.org/10.1145/1118299.1118443}, interhash = {13a63b658f968f61914e73fce28f9b19}, intrahash = {b7a7accbb0409b6f80f2056175dc1a80}, isbn = {0-7803-9451-8}, keywords = {dblp}, pages = {612-617}, publisher = {IEEE}, timestamp = {2019-09-27T13:56:34.000+0200}, title = {A novel instruction scratchpad memory optimization method based on concomitance metric.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#JanapsatyaIP06}, year = 2006 }