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Disambiguation of "Haque, Mohammad Shihabul"

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Rapid runtime estimation methods for pipelined MPSoCs.

, , , and . DATE, page 363-368. IEEE, (2010)

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Mohammad Ebrahimi University of Stuttgart

Mohammad Kasra Habib University of Stuttgart

Mohammad Youssef Mahfouz University of Stuttgart

Dorsa Mohammad Zaheri University of Stuttgart

Dr. rer. nat. Seyed Mohammad Mahdi Dadfar University of Stuttgart

 

Other publications of authors with the same name

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy., , , and . DATE, page 496-501. IEEE, (2010)DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs., , , , and . CODES+ISSS, page 151-160. ACM, (2012)CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique., , and . CoRR, (2015)SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy., , , and . DAC, page 356-361. ACM, (2010)CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique., , and . ICCAD, page 126-133. IEEE Computer Society, (2011)A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems., , , , , and . ISORC, page 116-123. IEEE Computer Society, (2018)Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems., , , and . IEEE Computer, 51 (11): 56-65 (2018)TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs., , , , and . CoRR, (2015)TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs., , , , and . ASP-DAC, page 320-325. IEEE, (2013)Rapid runtime estimation methods for pipelined MPSoCs., , , and . DATE, page 363-368. IEEE, (2010)