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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero. ISLPED, page 362-367. ACM, (2016)

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Dynamic Tolerance Region Computing for Multimedia.C. Álvarez, J. Corbal, and M. Valero. IEEE Trans. Computers, 61 (5): 650-665 (2012)Decoupled Vector Architectures.R. Espasa, and M. Valero. HPCA, page 281-290. IEEE Computer Society, (1996)A latency-conscious SMT branch prediction architecture.A. Falcón, O. Santana, A. Ramírez, and M. Valero. IJHPCN, 2 (1): 11-21 (2004)Access to streams in multiprocessor systems.M. Valero, M. Peiron, and E. Ayguadé. PDP, page 310-316. IEEE, (1993)Static Locality Analysis for Cache Management.F. Sánchez, A. González, and M. Valero. IEEE PACT, page 261-271. IEEE Computer Society, (1997)Virtual registers.A. González, M. Valero, J. González, and T. Arnal. HiPC, page 364-369. IEEE Computer Society, (1997)Automatic generation of loop scheduling for VLIW.C. Barrado, J. Labarta, E. Ayguadé, and M. Valero. PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.S. Isaza, F. Sánchez, G. Gaydadjiev, A. Ramírez, and M. Valero. SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Exploiting instruction- and data-level parallelism.R. Espasa, and M. Valero. IEEE Micro, 17 (5): 20-27 (1997)Multicore: The View from Europe.M. Valero, and N. Navarro. IEEE Micro, 30 (5): 2-4 (2010)

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Disambiguation of "Valero, Mateo"

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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

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Disambiguation of "Valero, Mateo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.