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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero. ISLPED, page 362-367. ACM, (2016)

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Automatic generation of loop scheduling for VLIW.C. Barrado, J. Labarta, E. Ayguadé, and M. Valero. PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.S. Isaza, F. Sánchez, G. Gaydadjiev, A. Ramírez, and M. Valero. SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Errata on "Measuring Experimental Error in Microprocessor Simulation".R. Desikan, D. Burger, S. Keckler, J. Cruz, F. Latorre, A. González, and M. Valero. SIGARCH Computer Architecture News, 30 (1): 2-4 (2002)Exploiting instruction- and data-level parallelism.R. Espasa, and M. Valero. IEEE Micro, 17 (5): 20-27 (1997)Multicore: The View from Europe.M. Valero, and N. Navarro. IEEE Micro, 30 (5): 2-4 (2010)Virtual registers.A. González, M. Valero, J. González, and T. Arnal. HiPC, page 364-369. IEEE Computer Society, (1997)Implicit Transactional Memory in Kilo-Instruction Multiprocessors.M. Galluzzi, E. Vallejo, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. Smith, and M. Valero. Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 339-353. Springer, (2007)Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies.I. Barrera, M. Moretó, E. Ayguadé, J. Labarta, M. Valero, and M. Casas. ICS, page 207-217. ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs.D. López, M. Valero, J. Llosa, and E. Ayguadé. International Conference on Supercomputing, page 12-19. ACM, (1997)Software trace cache.A. Ramírez, J. Larriba-Pey, C. Navarro, J. Torrellas, and M. Valero. International Conference on Supercomputing, page 119-126. ACM, (1999)

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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.