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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

, , , , , and . ISLPED, page 362-367. ACM, (2016)

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POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core., , , , , , and . PACT, page 447-448. ACM, (2016)Dynamic-vector execution on a general purpose EDGE chip multiprocessor., , , , , , , , and . ICSAMOS, page 18-25. IEEE, (2014)An Integrated Vector-Scalar Design on an In-Order ARM Core., , , , , , and . TACO, 14 (2): 17:1-17:26 (2017)Imposing coarse-grained reconfiguration to general purpose processors., , , , , , , and . SAMOS, page 42-51. IEEE, (2015)Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors., , , , , , , and . ISVLSI, page 19-26. IEEE Computer Society, (2015)Towards low-power embedded vector processor., , , , , and . Conf. Computing Frontiers, page 339-342. ACM, (2016)Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi., , , , , , and . HPCS, page 47-54. IEEE, (2014)A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques., , , , , and . ISLPED, page 362-367. ACM, (2016)On the selection of adder unit in energy efficient vector processing., , , , , and . ISQED, page 143-150. IEEE, (2013)VALib and SimpleVector: tools for rapid initial research on vector architectures., , , , , and . Conf. Computing Frontiers, page 7:1-7:10. ACM, (2014)