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A latency-conscious SMT branch prediction architecture.

A. Falcón, O. Santana, A. Ramírez, and M. Valero. IJHPCN, 2 (1): 11-21 (2004)

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Author retrospective for software trace cache.A. Ramírez, A. Falcón, O. Santana, and M. Valero. ICS 25th Anniversary, page 45-47. ACM, (2014)A latency-conscious SMT branch prediction architecture.A. Falcón, O. Santana, A. Ramírez, and M. Valero. IJHPCN, 2 (1): 11-21 (2004)Prophet/Critic Hybrid Branch Prediction.A. Falcón, J. Stark, A. Ramírez, K. Lai, and M. Valero. ISCA, page 250-263. IEEE Computer Society, (2004)COTSon: infrastructure for full system simulation.E. Argollo, A. Falcón, P. Faraboschi, M. Monchiero, and D. Ortega. Operating Systems Review, 43 (1): 52-61 (2009)Tolerating Branch Predictor Latency on SMT.A. Falcón, O. Santana, A. Ramírez, and M. Valero. ISHPC, volume 2858 of Lecture Notes in Computer Science, page 86-98. Springer, (2003)A Comprehensive Analysis of Indirect Branch Prediction.O. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramírez, and M. Valero. ISHPC, volume 2327 of Lecture Notes in Computer Science, page 133-145. Springer, (2002)Studying New Ways for Improving Adaptive History Length Branch Predictors.A. Falcón, O. Santana, P. Medina, E. Fernández, A. Ramírez, and M. Valero. ISHPC, volume 2327 of Lecture Notes in Computer Science, page 271-280. Springer, (2002)A Complexity-Effective Simultaneous Multithreading Architecture.C. Acosta, A. Falcón, A. Ramírez, and M. Valero. ICPP, page 157-164. IEEE Computer Society, (2005)Combining Simulation and Virtualization through Dynamic Sampling.A. Falcón, P. Faraboschi, and D. Ortega. ISPASS, page 72-83. IEEE Computer Society, (2007)Shared resource aware scheduling on power-constrained tiled many-core processors.S. Jha, W. Heirman, A. Falcón, J. Tubella, A. González, and L. Eeckhout. J. Parallel Distrib. Comput., (2017)

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A latency-conscious SMT branch prediction architecture.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A latency-conscious SMT branch prediction architecture.

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A latency-conscious SMT branch prediction architecture.