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Disambiguation of "Sinangil, Mahmut E."

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Self-aware computing in the Angstrom processor.

, , , , , , , , , , , and . DAC, page 259-264. ACM, (2012)

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E. Garrelts

E. Zafeiriou

P. E. Bl\"ochl

Andr{\'{e}} Buchau

Umm-E Habiba University of Stuttgart

 

Other publications of authors with the same name

An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access., and . ISSCC, page 318-319. IEEE, (2013)A 28nm 0.6V low-power DSP for mobile applications., , , , , , , , , and 5 other author(s). ISSCC, page 132-134. IEEE, (2011)A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (2): 557-567 (2016)Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems., , , , , and . IEEE Trans. on Circuits and Systems, 59-II (9): 533-537 (2012)Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard., , , and . J. Sel. Topics Signal Processing, 7 (6): 1017-1028 (2013)Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access., and . J. Solid-State Circuits, 49 (1): 107-117 (2014)A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination., , , , , , , , , and . J. Solid-State Circuits, 54 (1): 231-239 (2019)A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell., , , and . J. Solid-State Circuits, 54 (4): 1152-1160 (2019)A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS., , and . J. Solid-State Circuits, 44 (11): 3163-3173 (2009)Challenges and Directions for Low-Voltage SRAM., , and . IEEE Design & Test of Computers, 28 (1): 32-43 (2011)