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A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency., , and . ESSCIRC, page 271-274. IEEE, (2014)A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing., and . J. Solid-State Circuits, 49 (11): 2730-2739 (2014)A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip., , , , and . ESSCIRC, page 159-162. IEEE, (2011)EE2: Workshop on circuits for social good., , , , , , , , , and . ISSCC, page 523-525. IEEE, (2018)A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency., , and . J. Solid-State Circuits, 50 (7): 1540-1549 (2015)DCC: A Dependable Cache Coherence Multicore Architecture., , , and . IEEE Comput. Archit. Lett., 10 (1): 12-15 (2011)A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation., , , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)Self-aware computing in the Angstrom processor., , , , , , , , , and 2 other author(s). DAC, page 259-264. ACM, (2012)