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Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures., , and . Design Autom. for Emb. Sys., 4 (1): 5-22 (1999)Physical Unclonable Functions and Applications: A Tutorial., , , and . Proceedings of the IEEE, 102 (8): 1126-1141 (2014)AEGIS: A single-chip secure processor., , and . Inf. Sec. Techn. Report, 10 (2): 63-73 (2005)Topological Optimization of Multiple-Level Array Logic., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (6): 915-941 (1987)Challenges in code generation for embedded processors., , , , , , , and . Code Generation for Embedded Processors, page 48-64. Kluwer, (1994)MARTHA: architecture for control and emulation of power electronics and smart grid systems., , , and . DATE, page 519-524. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Integrity verification for path Oblivious-RAM., , , , and . HPEC, page 1-6. IEEE, (2013)Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching., , , , and . IEEE Trans. Emerging Topics Comput., 2 (1): 37-49 (2014)Solving covering problems using LPR-based lower bounds., , and . IEEE Trans. VLSI Syst., 8 (1): 9-17 (2000)A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation., , , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)