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A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.

Q. Dong, Z. Wang, J. Lim, Y. Zhang, M. Sinangil, Y. Shih, Y. Chih, J. Chang, D. Blaauw, und D. Sylvester. J. Solid-State Circuits, 54 (1): 231-239 (2019)

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Wei Yu University of Stuttgart

Zili Yu University of Stuttgart

Denis Dertli University of Stuttgart

Bo Hung Yu University of Stuttgart

Kateryna Derkach University of Stuttgart

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A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.Q. Dong, Z. Wang, J. Lim, Y. Zhang, M. Sinangil, Y. Shih, Y. Chih, J. Chang, D. Blaauw, und D. Sylvester. J. Solid-State Circuits, 54 (1): 231-239 (2019)A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.J. Yoon, M. Chang, W. Khwa, Y. Chih, M. Chang, und A. Raychowdhury. IEEE J. Solid State Circuits, 57 (1): 68-79 (2022)Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.M. Chang, J. Wu, T. Chien, Y. Liu, T. Yang, W. Shen, Y. King, C. Lin, K. Lin, Y. Chih und 1 andere Autor(en). J. Solid-State Circuits, 50 (11): 2786-2795 (2015)Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.M. Chang, C. Kuo, S. Sheu, C. Lin, Y. King, F. Chen, T. Ku, M. Tsai, J. Wu, und Y. Chih. J. Solid-State Circuits, 49 (4): 908-916 (2014)A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.M. Chang, C. Wu, C. Kuo, S. Shen, K. Lin, S. Yang, Y. King, C. Lin, und Y. Chih. ISSCC, Seite 434-436. IEEE, (2012)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.M. Chang, S. Shen, C. Liu, C. Wu, Y. Lin, S. Wu, C. Huang, H. Lai, Y. King, C. Lin und 3 andere Autor(en). ISSCC, Seite 206-208. IEEE, (2011)A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.C. Lo, W. Lin, W. Lin, H. Lin, T. Yang, Y. Chiang, Y. King, C. Lin, Y. Chih, T. Chang und 1 andere Autor(en). J. Solid-State Circuits, 54 (2): 584-595 (2019)Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.Y. Shih, C. Lee, Y. Chang, P. Lee, H. Lin, Y. Chen, K. Lin, T. Yeh, H. Yu, H. Chuang und 2 andere Autor(en). VLSI Circuits, Seite 79-80. IEEE, (2018)Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.C. Lai, C. Chou, C. Weng, Z. Lin, P. Tseng, C. Wang, C. Wang, C. Su, W. Chen, Y. Lin und 4 andere Autor(en). A-SSCC, Seite 13-16. IEEE, (2018)A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.M. Chang, C. Wu, C. Kuo, S. Shen, S. Yang, K. Lin, W. Shen, Y. King, C. Lin, und Y. Chih. J. Solid-State Circuits, 48 (9): 2250-2259 (2013)