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Disambiguation of "Chang, Jonathan"

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A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.

, , , , , , , , , and . J. Solid-State Circuits, 54 (1): 231-239 (2019)

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Jonathan Böhm University of Stuttgart

Jonathan Eck University of Stuttgart

Jonathan Villing University of Stuttgart

Jonathan Stober University of Stuttgart

Jonathan Skalden University of Stuttgart

 

Other publications of authors with the same name

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 42 (4): 846-852 (2007)A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell., , , and . J. Solid-State Circuits, 54 (4): 1152-1160 (2019)A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination., , , , , , , , , and . J. Solid-State Circuits, 54 (1): 231-239 (2019)Learning a Concept Hierarchy from Multi-labeled Documents., , , and . NIPS, page 3671-3679. (2014)Not-So-Latent Dirichlet Allocation: Collapsed Gibbs Sampling Using Human Judgments.. Mturk@HLT-NAACL, page 131-138. Association for Computational Linguistics, (2010)Comparison of child-human and child-computer interactions based on manual annotations., , , and . WOCCI, page 49-54. ISCA, (2009)12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , and 4 other author(s). ISSCC, page 210-211. IEEE, (2017)Automatic Instruction-Level Software-Only Recovery., , and . IEEE Micro, 27 (1): 36-47 (2007)A 45 nm 8-Core Enterprise Xeon¯ Processor., , , , , , , , , and . J. Solid-State Circuits, 45 (1): 7-14 (2010)A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 50 (1): 170-177 (2015)