%0 Journal Article %1 journals/jssc/SinangilLLC19 %A Sinangil, Mahmut E. %A Lin, Yen-Ting %A Liao, Hung-Jen %A Chang, Jonathan %D 2019 %J J. Solid-State Circuits %K dblp %N 4 %P 1152-1160 %T A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. %U http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SinangilLLC19 %V 54

@article{journals/jssc/SinangilLLC19, added-at = {2019-04-12T00:00:00.000+0200}, author = {Sinangil, Mahmut E. and Lin, Yen-Ting and Liao, Hung-Jen and Chang, Jonathan}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27d45dec42661ba58f0c4f6ab67297094/dblp}, ee = {https://doi.org/10.1109/JSSC.2019.2895236}, interhash = {f7b89e47f479af73c1c25fb908efabe4}, intrahash = {7d45dec42661ba58f0c4f6ab67297094}, journal = {J. Solid-State Circuits}, keywords = {dblp}, number = 4, pages = {1152-1160}, timestamp = {2019-09-27T06:09:34.000+0200}, title = {A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SinangilLLC19}, volume = 54, year = 2019 }