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Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale.

, , , , , and . Microelectronics Reliability, 49 (9-11): 1188-1191 (2009)

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Influence of a low field with opposite polarity to the stress on the degradation of 4.5 nm thick SiO2 films., , , and . Microelectronics Reliability, 41 (7): 1011-1013 (2001)Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale., , , and . Microelectronics Reliability, 45 (9-11): 1390-1393 (2005)Threshold voltage and on-current Variability related to interface traps spatial distribution., , , , , , , , and . ESSDERC, page 230-233. IEEE, (2015)UHV CAFM characterization of high-k dielectrics: Effect of the technique resolution on the pre- and post-breakdown electrical measurements., , , , , and . Microelectronics Reliability, 50 (9-11): 1312-1315 (2010)Threading dislocations in III-V semiconductors: Analysis of electrical conduction., , , , , , , , , and . IRPS, page 4. IEEE, (2015)Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale., , , , , and . Microelectronics Reliability, 49 (9-11): 1188-1191 (2009)Standard and C-AFM tests to study the post-BD gate oxide conduction of MOS devices after current limited stresses., , , and . Microelectronics Reliability, 44 (9-11): 1523-1528 (2004)Oxide conductivity increase during the progressive-breakdown of SiO2 gate oxides observed with C-AFM., , and . Microelectronics Reliability, 43 (9-11): 1501-1505 (2003)Influence of the manufacturing process on the electrical properties of thin (k stacks observed with CAFM., , , , , , , and . Microelectronics Reliability, 47 (9-11): 1424-1428 (2007)Nanoscale and device level electrical behavior of annealed ALD Hf-based gate oxide stacks grown with different precursors., , , , , , and . Microelectronics Reliability, 53 (6): 867-871 (2013)