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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)SUB-45nm Technology and Design Challenges., , and . ISQED, page 3. IEEE Computer Society, (2007)8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating., , , , , , , , and . ISSCC, page 152-153. IEEE, (2016)Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses., , , , , and . ISCAS (1), page 592-595. IEEE, (2005)Characterization of Inverse Temperature Dependence in logic circuits., , , , , and . CICC, page 1-4. IEEE, (2012)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)SUB 45nm Low Power Design Challenges.. ISQED, page 4. IEEE Computer Society, (2007)A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors., , , , , , , and . ICCD, page 253-257. IEEE Computer Society, (2005)Formal derivation of optimal active shielding for low-power on-chip buses., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (5): 821-836 (2006)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)