Author of the publication

TX Equalization Scheme.

D. Kim, M. Park, S. Jang, J. Song, H. Chi, G. Choi, S. Choi, J. Kim, C. Kim, K. Kim, K. Koo, S. Song, Y. Kim, D. Lee, J. Lee, D. Kim, K. Kwon, M. Han, B. Choi, H. Kim, S. Ku, Y. Kim, J. Kim, S. Kim, Y. Seo, S. Oh, D. Im, H. Kim, J. Choi, J. Chung, C. Lee, Y. Lee, J. Cho, J. Chun, and J. Oh. ISSCC, page 380-382. IEEE, (2019)

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Phi-Long Chung University of Stuttgart

Other publications of authors with the same name

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller.S. Lee, B. Jeon, K. Kang, D. Ka, N. Kim, Y. Kim, Y. Hong, M. Kang, J. Min, M. Lee and 19 other author(s). ISSCC, page 384-386. IEEE, (2019)A Compact Resistor-Based CMOS Temperature Sensor With an Inaccuracy of 0.12 °C (3σ) and a Resolution FoM of 0.43 pJ⋅K2 in 65-nm CMOS.W. Choi, Y. Lee, S. Kim, S. Lee, J. Jang, J. Chun, K. Makinwa, and Y. Chae. J. Solid-State Circuits, 53 (12): 3356-3367 (2018)A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.D. Kim, M. Park, S. Jang, J. Song, H. Chi, G. Choi, S. Choi, J. Kim, C. Kim, K. Kim and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS.W. Choi, Y. Lee, S. Kim, S. Lee, J. Jang, J. Chun, K. Makinwa, and Y. Chae. ISSCC, page 322-324. IEEE, (2018)A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.J. Kang, J. Yang, K. Kim, J. Chae, G. Lee, S. Byeon, B. Kim, D. Kim, Y. Kim, Y. Cho and 14 other author(s). IEEE J. Solid State Circuits, 57 (1): 212-223 (2022)A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.D. Kim, K. Koo, Y. Kim, D. Lee, J. Lee, K. Kwon, B. Choi, H. Kim, S. Ku, J. Kim and 15 other author(s). J. Solid-State Circuits, 55 (1): 167-177 (2020)

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Disambiguation of "Chun, Junhyun"

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A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.

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Phi-Long Chung University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chun, Junhyun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.

Please choose a person to relate this publication to

Phi-Long Chung University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.